H.265 (High Efficiency Video Coding)

H.265 encoder and decoder.

HEVC substantially improves coding efficiency as compared to AVC High Profile (H.264), reducing the bit rate requirements by half with comparable image quality, with the expense of increased computational complexity, hence area. Adapt-IP is able to deliver an HEVC core, trading off computational complexity, compression rate, robustness to errors, and processing delay time versus area.

HEVC is targeted at next-generation HDTV displays and content capture systems which feature progressive scanned frame rates and display resolutions from QVGA (320×240) up to 1080p (1920×1080) and 4320p (7680×4320), as well as improved picture quality in terms of noise level, color gamut, and dynamic range.

The core comes with working / useful firmware to implement an encoder, or a decoder, with associated Windows device driver and test application.

Both the encoder and decoder have bus master AXI interfaces to provide maximum throughput with minimal process intervention.

Coded in System C and built with the Forte HLS tool, user customization is readily available.

Adapt-IP's H.265 cores can be ordered in the following configurations:
  • SystemC model for inclusion in a virtual platform system model
  • Synthesizable Verilog RTL for implementation in an FPGA or ASIC
    • For ASIC, specify the required technology (.lib file)
  • Test board with the core(s) implemented in an FGPA, with firmware loaded into the board's flash memory
  • Customized core
    • Adapt IP can customize the core to meet nearly any customer requirement

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